1. Field of the Invention
This invention is related to the field of processors and, more particularly, to register renaming features of processors.
2. Description of the Related Art
Superscalar processors attempt to achieve high performance by issuing and executing multiple instructions per clock cycle and by employing the highest possible clock frequency consistent with the design. One method for increasing the number of instructions executed per clock cycle is out of order execution. In out of order execution, instructions may be executed in a different order than that specified in the program sequence (or "program order"). Certain instructions near each other in a program sequence may have dependencies which prohibit their concurrent execution, while subsequent instructions in the program sequence may not have dependencies on the previous instructions. Accordingly, out of order execution may increase performance of the superscalar processor by increasing the number of instructions executed concurrently (on the average).
Unfortunately, out of order execution presents additional hardware complexities for the processor. For example, a second instruction which is subsequent to a first instruction in program order may update a storage location which is read by the first instruction. In other words, the destination operand of the second instruction may be one of the source operands of the first instruction. For proper program execution, the first instruction must receive, as a source operand, the value stored in the storage location prior to execution of the second instruction. Similarly, if the first and second instructions have a particular storage location as the destination operand, the result of the second instruction should be the value stored in the storage location subsequent to executing both the first and second instructions (and prior to executing a third instruction which updates the storage location).
Generally, instructions may have one or more source operands and one or more destination operands. The source operands are input values to be manipulated according to the instruction definition to produce one or more results (which are the destination operands). Source and destination operands may be memory operands stored in a memory location external to the processor, or may be register operands stored in register storage locations included within the processor. The instruction set architecture employed by the processor defines a number of architected registers. These registers are defined to exist by the instruction set architecture, and instructions may be coded to use the architected registers as source and destination operands. An instruction specifies a particular register as a source or destination operand via a register number (or register address) in an operand field of the instruction. The register number uniquely identifies the selected register among the architected registers. A source operand is identified by a source register number and a destination operand is identified by a destination register number.
In addition to the architected registers, some processors define additional microarchitected registers which may be used to hold temporary results during instruction execution. For example, some processors use microcoding techniques to handle the most complex instructions. Microcode routines are executed in response to the complex instructions and include a plurality of simpler instructions. The microcode routines may generate temporary results while executing the complex instruction. These microarchitected registers (or temporary registers) are assigned additional register numbers to identify the temporary registers uniquely from the architected registers. Together, the architected registers and temporary registers are referred to herein as logical registers.
A processor employing out of order execution may experience the above hazards with respect to register operands. A method for handling these hazards is register renaming. In register renaming, the processor implements a set of physical registers. The number of physical registers is greater than the number of logical registers specified by the instruction set architecture and microarchitecture of the processor. As instructions arc issued, physical registers are assigned to the destination register operands of the instructions. A physical register number identifying the assigned physical register is provided for each destination operand, and an indication of which physical registers correspond to the logical registers is maintained by the processor. Subsequent instructions which have the logical registers as source operands are provided with the corresponding physical register number for reading the appropriate source operand. By assigning different physical registers to store the destination operands of each instruction, instructions may freely update their destination operands in any order, since different physical storage locations are being updated.
Unfortunately, the process of assigning physical register numbers to destination operands instructions and providing those physical register numbers to subsequent instructions having the destination operands as source operands may be complex and slow. Particularly difficult in superscalar processors is the assignment of physical register numbers to destination operands of instructions and providing the physical register numbers to subsequent dependent instructions which are passing through the register renaming hardware simultaneously with those instructions. A register renaming structure which may operate at higher frequency yet still handle renaming of multiple instructions per clock cycle is desired.
Register renaming presents difficulties when instructions experience exception conditions. As used herein, an exception refers to an error in the execution of instructions which requires subsequent instructions to be discarded and instruction fetch to be started at a different address. For example, branch misprediction is an exception condition. Processors may perform branch prediction to speculatively fetch, issue, and execute instructions subsequent to conditional branch instructions. If the prediction is incorrect, the instructions subsequent to the branch instruction are discarded and instructions are fetched according to execution of the branch instruction. Additional exception conditions may include address translation errors for addresses of memory operands and other architectural or microarchitectural error conditions.
Because register renaming may have been applied to instructions which are subsequently discarded due to an exception, the mapping of logical registers to physical registers must be recovered to a state consistent with the instruction experiencing the exception. In other words, the mapping of logical registers to physical registers should reflect the execution of instructions prior to the instruction experiencing the exception (in program order) and not reflect the execution of instructions subsequent to the instruction experiencing the exception. It is desirable for the recovery of the register rename map to be rapid so that instructions fetched in response to the exception may pass through the register renaming hardware as soon as they are available. If recovery of the register rename map is still occurring when newly fetched instructions reach the register renaming hardware, then the newly fetched instructions must be stalled until the register rename map is recovered. Performance of the processor are is thereby lost.
Still further, register renaming hardware generally includes a mechanism for reusing physical registers previously assigned to a destination operand of a particular instruction once the corresponding logical register has been committed to a value corresponding to a subsequent instruction. It is desirable to use the physical registers as efficiently as possible, and to also providing accurate method for freeing the physical registers once the subsequent state has been committed to the corresponding logical register.